Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. ... Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)		2019-02-25 16:18:13 -08:00
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.gitignore	Progress in FIRRTL back-end	2016-11-18 00:32:35 +01:00
firrtl.cc	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
Makefile.inc	Added first draft of FIRRTL back-end	2016-11-17 23:36:47 +01:00
test.sh	More progress on Firrtl backend.	2017-02-13 11:17:53 -08:00
test.v	More progress on Firrtl backend.	2017-02-13 11:17:53 -08:00