Adam Greig 9e02786d39 Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.		2021-05-12 10:04:34 +01:00
..
tests
.gitignore
arith_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
brams.txt
brams_connect.py
brams_init.py
brams_map.v	remove unused parameters	2020-03-06 16:45:36 +01:00
cells_bb.v	Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.	2021-05-12 10:04:34 +01:00
cells_ff.vh
cells_io.vh
cells_map.v	ecp5: Use dfflegalize.	2020-07-05 18:49:41 +02:00
cells_sim.v	ecp5: TRELLIS_FF bypass path only in async mode	2020-05-14 10:33:56 -07:00
dsp_map.v	ecp5: Force SIGNED ports to be 1 bit	2020-04-16 16:38:19 +01:00
ecp5_gsr.cc	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
latches_map.v
lutrams.txt
lutrams_map.v
Makefile.inc	ecp5: Use dfflegalize.	2020-07-05 18:49:41 +02:00
synth_ecp5.cc	Blackbox all whiteboxes after synthesis	2021-03-17 21:07:20 +00:00