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https://github.com/YosysHQ/yosys
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72787f52fc
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
93 lines
2.8 KiB
C++
93 lines
2.8 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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int lut2mux(Cell *cell)
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{
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_y = cell->getPort(ID::Y);
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Const lut = cell->getParam(ID::LUT);
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int count = 1;
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if (GetSize(sig_a) == 1)
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{
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cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
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}
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else
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{
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SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
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SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
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SigSpec sig_y1 = cell->module->addWire(NEW_ID);
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SigSpec sig_y2 = cell->module->addWire(NEW_ID);
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Const lut1 = lut.extract(0, GetSize(lut)/2);
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Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
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count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
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count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
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cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
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}
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cell->module->remove(cell);
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return count;
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}
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struct Lut2muxPass : public Pass {
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Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" lut2mux [options] [selection]\n");
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log("\n");
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log("This pass converts $lut cells to $_MUX_ gates.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-v") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : module->selected_cells()) {
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if (cell->type == ID($lut)) {
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IdString cell_name = cell->name;
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int count = lut2mux(cell);
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log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
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}
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}
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}
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} Lut2muxPass;
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PRIVATE_NAMESPACE_END
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