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30 lines
619 B
Plaintext
30 lines
619 B
Plaintext
read_rtlil <<EOT
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# Generated by Yosys 0.16+61 (git sha1 3730db4b9, clang 13.0.1 -fPIC -Os)
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autoidx 16887
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attribute \blackbox 1
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module \TRELLIS_IO
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parameter \DIR
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wire inout 1 \B
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wire input 2 \I
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wire output 3 \O
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wire input 4 \T
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end
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attribute \top 1
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module \icesugarpro_top
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wire width 8 inout 1 \P5_pmod_low
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attribute \hdlname "vt spi 1796"
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cell $_DFF_PP0_ $auto$ff.cc:262:slice$16873
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connect \C 1'x
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connect \D 1'x
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connect \Q \P5_pmod_low [3]
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connect \R 1'x
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end
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connect \P5_pmod_low [7:4] 4'x
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end
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EOT
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read_verilog -lib -specify +/ecp5/cells_sim.v
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techmap -map +/ecp5/cells_map.v
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abc9
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