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19 lines
530 B
Verilog
19 lines
530 B
Verilog
`default_nettype none
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module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
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(input wire clk,
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input wire [CTRLW-1:0] ctrl,
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input wire [DINW-1:0] din,
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input wire en,
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output reg [WIDTH-1:0] dout);
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reg [SELW:0] sel;
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localparam SLICE = WIDTH/(SELW**2);
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always @(posedge clk)
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begin
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if (en) begin
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for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
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dout[(ctrl*sel)+:SLICE] <= din;
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end
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end
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endmodule
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