yosys/tests/sva/nested_clk_else.sv at c9488c4fd0c398ee68333936563a00d6646175f3 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00

Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures

For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.

2022-05-03 14:13:08 +02:00

11 lines

241 B

Systemverilog

Raw Blame History

 module top (input clk, a, b);
 	always @(posedge clk) begin
         if (a);
         else assume property (@(posedge clk) b);
 	end
 `ifndef FAIL
     assume property (@(posedge clk) !a);
 `endif
     assert property (@(posedge clk) b);
 endmodule