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71e7e09092
This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog.
45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
// Some strict implementatins either forbid hierarchical identifiers within
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// constant expressions, or forbid declaring functions in generate blocks, or
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// both. Yosys and Iverilog are not strict in either of these ways.
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module module_scope_func_top(
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input wire inp,
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output wire [31:0] out1, out2, out4, out5, out7, out8,
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output reg [31:0] out3, out6, out9
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);
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function automatic integer incr;
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input integer value;
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incr = value + 1;
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endfunction
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task send;
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output integer out;
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out = 55;
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endtask
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assign out1 = module_scope_func_top.incr(inp);
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localparam C = module_scope_func_top.incr(10);
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assign out2 = C;
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initial module_scope_func_top.send(out3);
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if (1) begin : blk
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// shadows module_scope_func_top.incr
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function automatic integer incr;
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input integer value;
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incr = value * 2;
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endfunction
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// shadows module_scope_func_top.send
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task send;
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output integer out;
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out = 66;
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endtask
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assign out4 = module_scope_func_top.incr(inp);
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localparam D = module_scope_func_top.incr(20);
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assign out5 = D;
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initial module_scope_func_top.send(out6);
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assign out7 = incr(inp);
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localparam E = incr(30);
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assign out8 = E;
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initial send(out9);
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end
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endmodule
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