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18 lines
293 B
Verilog
18 lines
293 B
Verilog
`default_nettype none
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module genblk_order_top(
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output wire out1,
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output wire out2
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);
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generate
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if (1) begin : outer
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if (1) begin : foo
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wire x = 0;
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if (1) begin : foo
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wire x = 1;
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assign out1 = foo.x;
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end
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assign out2 = foo.x;
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end
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end
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endgenerate
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endmodule
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