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21 lines
360 B
Verilog
21 lines
360 B
Verilog
module latchp ( input d, clk, en, output reg q );
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always @*
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if ( en )
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q <= d;
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endmodule
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module latchn ( input d, clk, en, output reg q );
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always @*
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if ( !en )
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q <= d;
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endmodule
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module latchsr ( input d, clk, en, clr, pre, output reg q );
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always @*
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if ( clr )
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q <= 1'b0;
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else if ( pre )
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q <= 1'b1;
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else if ( en )
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q <= d;
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endmodule
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