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51 lines
1.6 KiB
Verilog
51 lines
1.6 KiB
Verilog
module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3;
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parameter IDLE = 3'b001;
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parameter GNT0 = 3'b010;
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parameter GNT1 = 3'b100;
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parameter GNT2 = 3'b101;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end
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else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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