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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
62 lines
2 KiB
C++
62 lines
2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef ABC_AIGERPARSE
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#define ABC_AIGERPARSE
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct AigerReader
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{
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RTLIL::Design *design;
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std::istream &f;
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RTLIL::IdString clk_name;
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RTLIL::Module *module;
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std::string map_filename;
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bool wideports;
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const int aiger_autoidx;
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unsigned M, I, L, O, A;
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unsigned B, C, J, F; // Optional in AIGER 1.9
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unsigned line_count;
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uint32_t piNum, flopNum;
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std::vector<RTLIL::Wire*> inputs;
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std::vector<RTLIL::Wire*> latches;
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std::vector<RTLIL::Wire*> outputs;
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std::vector<RTLIL::Wire*> bad_properties;
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std::vector<RTLIL::Cell*> boxes;
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std::vector<int> mergeability, initial_state;
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AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
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void parse_aiger();
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void parse_xaiger();
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void parse_aiger_ascii();
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void parse_aiger_binary();
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void post_process();
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RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal);
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};
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YOSYS_NAMESPACE_END
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#endif
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