3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00
yosys/tests/verific/bounds.ys
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-09-10 12:52:42 +02:00

6 lines
228 B
Plaintext

read -vhdl bounds.vhd
verific -import work
select -assert-count 1 a:bottom_bound=5'bs11011
select -assert-count 1 a:top_bound=5'bs01010
select -assert-count 1 a:bottom_bound=5'bs11010
select -assert-count 1 a:top_bound=5'bs01011