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55dc5a4e4f
* xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
328 lines
7.4 KiB
Verilog
328 lines
7.4 KiB
Verilog
module abc9_test001(input a, output o);
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assign o = a;
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endmodule
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module abc9_test002(input [1:0] a, output o);
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assign o = a[1];
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endmodule
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module abc9_test003(input [1:0] a, output [1:0] o);
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assign o = a;
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endmodule
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module abc9_test004(input [1:0] a, output o);
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assign o = ^a;
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endmodule
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module abc9_test005(input [1:0] a, output o, output p);
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assign o = ^a;
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assign p = ~o;
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endmodule
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module abc9_test006(input [1:0] a, output [2:0] o);
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assign o[0] = ^a;
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assign o[1] = ~o[0];
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assign o[2] = o[1];
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endmodule
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module abc9_test007(input a, output o);
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wire b, c;
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assign c = ~a;
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assign b = c;
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abc9_test007_sub s(b, o);
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endmodule
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module abc9_test007_sub(input a, output b);
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assign b = a;
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endmodule
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module abc9_test008(input a, output o);
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wire b, c;
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assign b = ~a;
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assign c = b;
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abc9_test008_sub s(b, o);
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endmodule
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module abc9_test008_sub(input a, output b);
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assign b = ~a;
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endmodule
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module abc9_test009(inout io, input oe);
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reg latch;
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always @(io or oe)
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if (!oe)
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latch <= io;
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assign io = oe ? ~latch : 1'bz;
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endmodule
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module abc9_test010(inout [7:0] io, input oe);
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reg [7:0] latch;
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always @(io or oe)
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if (!oe)
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latch <= io;
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assign io = oe ? ~latch : 8'bz;
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endmodule
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module abc9_test011(inout io, input oe);
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reg latch;
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always @(io or oe)
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if (!oe)
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latch <= io;
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//assign io = oe ? ~latch : 8'bz;
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endmodule
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module abc9_test012(inout io, input oe);
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reg latch;
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//always @(io or oe)
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// if (!oe)
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// latch <= io;
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assign io = oe ? ~latch : 8'bz;
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endmodule
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module abc9_test013(inout [3:0] io, input oe);
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reg [3:0] latch;
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always @(io or oe)
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if (!oe)
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latch[3:0] <= io[3:0];
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else
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latch[7:4] <= io;
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assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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endmodule
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module abc9_test014(inout [7:0] io, input oe);
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abc9_test012_sub sub(io, oe);
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endmodule
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module abc9_test012_sub(inout [7:0] io, input oe);
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reg [7:0] latch;
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always @(io or oe)
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if (!oe)
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latch[3:0] <= io;
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else
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latch[7:4] <= io;
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assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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endmodule
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module abc9_test015(input a, output b, input c);
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assign b = ~a;
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(* keep *) wire d;
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assign d = ~c;
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endmodule
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module abc9_test016(input a, output b);
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assign b = ~a;
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(* keep *) reg c;
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always @* c <= ~a;
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endmodule
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module abc9_test017(input a, output b);
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assign b = ~a;
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(* keep *) reg c;
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always @* c = b;
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endmodule
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module abc9_test018(input a, output b, output c);
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assign b = ~a;
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(* keep *) wire [1:0] d;
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assign c = &d;
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endmodule
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module abc9_test019(input a, output b);
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assign b = ~a;
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(* keep *) reg [1:0] c;
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reg d;
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always @* d <= &c;
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endmodule
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module abc9_test020(input a, output b);
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assign b = ~a;
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(* keep *) reg [1:0] c;
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(* keep *) reg d;
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always @* d <= &c;
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endmodule
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// Citation: https://github.com/alexforencich/verilog-ethernet
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module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
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input clk;
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output [47:0] m_eth_dest_mac;
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input m_eth_hdr_ready;
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output m_eth_hdr_valid;
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output [7:0] m_eth_payload_axis_tdata;
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output [7:0] m_eth_payload_axis_tdest;
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output [7:0] m_eth_payload_axis_tid;
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output m_eth_payload_axis_tkeep;
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output m_eth_payload_axis_tlast;
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input m_eth_payload_axis_tready;
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output m_eth_payload_axis_tuser;
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output m_eth_payload_axis_tvalid;
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output [47:0] m_eth_src_mac;
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output [15:0] m_eth_type;
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input rst;
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input [191:0] s_eth_dest_mac;
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output [3:0] s_eth_hdr_ready;
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input [3:0] s_eth_hdr_valid;
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input [31:0] s_eth_payload_axis_tdata;
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input [31:0] s_eth_payload_axis_tdest;
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input [31:0] s_eth_payload_axis_tid;
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input [3:0] s_eth_payload_axis_tkeep;
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input [3:0] s_eth_payload_axis_tlast;
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output [3:0] s_eth_payload_axis_tready;
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input [3:0] s_eth_payload_axis_tuser;
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input [3:0] s_eth_payload_axis_tvalid;
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input [191:0] s_eth_src_mac;
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input [63:0] s_eth_type;
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(* keep *)
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wire [0:0] grant, request;
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wire a;
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not u0 (
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a,
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grant[0]
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);
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and u1 (
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request[0],
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s_eth_hdr_valid[0],
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a
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);
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(* keep *)
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MUXF8 u2 (
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.I0(1'bx),
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.I1(1'bx),
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.O(o),
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.S(1'bx)
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);
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arbiter arb_inst (
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.acknowledge(acknowledge),
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.clk(clk),
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.grant(grant),
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.grant_encoded(grant_encoded),
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.grant_valid(grant_valid),
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.request(request),
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.rst(rst)
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);
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endmodule
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module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
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input [3:0] acknowledge;
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input clk;
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output [3:0] grant;
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output [1:0] grant_encoded;
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output grant_valid;
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input [3:0] request;
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input rst;
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endmodule
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(* abc9_box, blackbox *)
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module MUXF8(input I0, I1, S, output O);
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specify
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(I0 => O) = 0;
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(I1 => O) = 0;
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(S => O) = 0;
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endspecify
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endmodule
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// Citation: https://github.com/alexforencich/verilog-ethernet
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module abc9_test022
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(
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input wire clk,
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input wire i,
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output wire [7:0] m_eth_payload_axis_tkeep
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);
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reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
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assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
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always @(posedge clk)
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m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
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endmodule
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// Citation: https://github.com/riscv/riscv-bitmanip
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module abc9_test023 #(
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parameter integer N = 2,
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parameter integer M = 2
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) (
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input [7:0] din,
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output [M-1:0] dout
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);
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wire [2*M-1:0] mask = {M{1'b1}};
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assign dout = (mask << din[N-1:0]) >> M;
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endmodule
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module abc9_test024(input [3:0] i, output [3:0] o);
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abc9_test024_sub a(i[1:0], o[1:0]);
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endmodule
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module abc9_test024_sub(input [1:0] i, output [1:0] o);
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assign o = i;
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endmodule
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module abc9_test025(input [3:0] i, output [3:0] o);
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abc9_test024_sub a(i[2:1], o[2:1]);
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endmodule
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module abc9_test026(output [3:0] o, p);
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assign o = { 1'b1, 1'bx };
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assign p = { 1'b1, 1'bx, 1'b0 };
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endmodule
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module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
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always @*
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if (en)
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q <= d;
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endmodule
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module abc9_test031(input clk1, clk2, d, output reg q1, q2);
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always @(posedge clk1) q1 <= d;
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always @(negedge clk2) q2 <= q1;
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endmodule
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module abc9_test032(input clk, d, r, output reg q);
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always @(posedge clk or posedge r)
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if (r) q <= 1'b0;
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else q <= d;
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endmodule
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module abc9_test033(input clk, d, r, output reg q);
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always @(negedge clk or posedge r)
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if (r) q <= 1'b1;
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else q <= d;
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endmodule
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module abc9_test034(input clk, d, output reg q1, q2);
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always @(posedge clk) q1 <= d;
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always @(posedge clk) q2 <= q1;
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endmodule
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module abc9_test035(input clk, d, output reg [1:0] q);
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always @(posedge clk) q[0] <= d;
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always @(negedge clk) q[1] <= q[0];
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endmodule
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module abc9_test036(input A, B, S, output [1:0] O);
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(* keep *)
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MUXF8 m (
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.I0(A),
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.I1(B),
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.O(O[0]),
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.S(S)
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);
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MUXF8 m2 (
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.I0(A),
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.I1(B),
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.O(O[1]),
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.S(S)
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);
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endmodule
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(* abc9_box, whitebox *)
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module MUXF7(input I0, I1, S, output O);
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assign O = S ? I1 : I0;
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specify
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(I0 => O) = 0;
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(I1 => O) = 0;
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(S => O) = 0;
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endspecify
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endmodule
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module abc9_test037(output o);
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MUXF7 m(.I0(1'b1), .I1(1'b0), .S(o), .O(o));
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endmodule
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