mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
130 lines
3.9 KiB
C++
130 lines
3.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct InsbufPass : public Pass {
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InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
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void help() override
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{
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log("\n");
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log(" insbuf [options] [selection]\n");
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log("\n");
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log("Insert buffer cells into the design for directly connected wires.\n");
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log("\n");
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log(" -buf <celltype> <in-portname> <out-portname>\n");
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log(" Use the given cell type instead of $_BUF_. (Notice that the next\n");
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log(" call to \"clean\" will remove all $_BUF_ in the design.)\n");
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log("\n");
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log(" -chain\n");
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log(" Chain buffer cells\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
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IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
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bool chain_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-buf" && argidx+3 < args.size()) {
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celltype = RTLIL::escape_id(args[++argidx]);
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in_portname = RTLIL::escape_id(args[++argidx]);
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out_portname = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (arg == "-chain") {
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chain_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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std::vector<RTLIL::SigSig> new_connections;
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pool<Cell*> bufcells;
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SigMap sigmap;
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for (auto &conn : module->connections())
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{
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RTLIL::SigSig new_conn;
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for (int i = 0; i < GetSize(conn.first); i++)
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{
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SigBit lhs = conn.first[i];
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SigBit rhs = conn.second[i];
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if (!lhs.wire || !design->selected(module, lhs.wire)) {
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new_conn.first.append(lhs);
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new_conn.second.append(rhs);
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log("Skip %s: %s -> %s\n", log_id(module), log_signal(rhs), log_signal(lhs));
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continue;
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}
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if (chain_mode && rhs.wire) {
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rhs = sigmap(rhs);
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SigBit outbit = sigmap(lhs);
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sigmap.add(lhs, rhs);
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sigmap.add(outbit);
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}
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Cell *cell = module->addCell(NEW_ID, celltype);
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cell->setPort(in_portname, rhs);
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cell->setPort(out_portname, lhs);
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log("Add %s/%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
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bufcells.insert(cell);
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}
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if (GetSize(new_conn.first))
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new_connections.push_back(new_conn);
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}
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if (chain_mode) {
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for (auto &cell : module->selected_cells()) {
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if (bufcells.count(cell))
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continue;
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for (auto &port : cell->connections())
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if (cell->input(port.first)) {
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auto s = sigmap(port.second);
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if (s == port.second)
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continue;
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log("Rewrite %s/%s/%s: %s -> %s\n", log_id(module), log_id(cell),
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log_id(port.first), log_signal(port.second), log_signal(s));
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cell->setPort(port.first, s);
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}
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}
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}
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module->new_connections(new_connections);
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}
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}
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} InsbufPass;
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PRIVATE_NAMESPACE_END
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