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yosys/techlibs/intel
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Catherine a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
..
common
cyclone10lp
cycloneiv
cycloneive
max10 Removed SystemVerilog module end label 2024-03-19 01:31:36 +01:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
synth_intel.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00