mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
19 lines
383 B
Systemverilog
19 lines
383 B
Systemverilog
import package_import_separate::*;
|
|
|
|
module package_import_separate_module;
|
|
logic [DATAWIDTH-1:0] data;
|
|
logic [ADDRWIDTH-1:0] addr;
|
|
logic [2:0] state;
|
|
|
|
always_comb begin
|
|
case (state)
|
|
IDLE: data = 8'h00;
|
|
START: data = 8'h01;
|
|
DATA: data = 8'h02;
|
|
STOP: data = 8'h04;
|
|
DONE: data = 8'h05;
|
|
default: data = 8'hFF;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|