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https://github.com/YosysHQ/yosys
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5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
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// test_simulation_shifter_left_16_test.v
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module f1_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
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assign OUT = IN << SHIFT;
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endmodule
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// test_simulation_shifter_left_32_test.v
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module f2_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
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assign OUT = IN << SHIFT;
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endmodule
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// test_simulation_shifter_left_4_test.v
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module f3_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
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assign OUT = IN << SHIFT;
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endmodule
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// test_simulation_shifter_left_64_test.v
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module f4_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
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assign OUT = IN << SHIFT;
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endmodule
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// test_simulation_shifter_left_8_test.v
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module f5_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
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assign OUT = IN << SHIFT;
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endmodule
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// test_simulation_shifter_right_16_test.v
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module f6_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
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assign OUT = IN >> SHIFT;
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endmodule
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// test_simulation_shifter_right_32_test.v
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module f7_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
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assign OUT = IN >> SHIFT;
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endmodule
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// test_simulation_shifter_right_4_test.v
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module f8_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
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assign OUT = IN >> SHIFT;
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endmodule
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// test_simulation_shifter_right_64_test.v
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module f9_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
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assign OUT = IN >> SHIFT;
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endmodule
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// test_simulation_shifter_right_8_test.v
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module f10_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
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assign OUT = IN >> SHIFT;
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endmodule
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