mirror of
https://github.com/YosysHQ/yosys
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5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
176 lines
3.7 KiB
Verilog
176 lines
3.7 KiB
Verilog
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// test_simulation_mux_16_test.v
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module f1_test(input [15:0] in, input [3:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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8: out = in[8];
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9: out = in[9];
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10: out = in[10];
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11: out = in[11];
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12: out = in[12];
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13: out = in[13];
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14: out = in[14];
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15: out = in[15];
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endcase
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endmodule
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// test_simulation_mux_2_test.v
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module f2_test(input [1:0] in, input select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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endcase
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endmodule
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// test_simulation_mux_32_test.v
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module f3_test(input [31:0] in, input [4:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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8: out = in[8];
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9: out = in[9];
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10: out = in[10];
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11: out = in[11];
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12: out = in[12];
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13: out = in[13];
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14: out = in[14];
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15: out = in[15];
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16: out = in[16];
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17: out = in[17];
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18: out = in[18];
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19: out = in[19];
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20: out = in[20];
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21: out = in[21];
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22: out = in[22];
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23: out = in[23];
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24: out = in[24];
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25: out = in[25];
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26: out = in[26];
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27: out = in[27];
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28: out = in[28];
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29: out = in[29];
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30: out = in[30];
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31: out = in[31];
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endcase
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endmodule
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// test_simulation_mux_4_test.v
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module f4_test(input [3:0] in, input [1:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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endcase
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endmodule
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// test_simulation_mux_64_test.v
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module f5_test(input [63:0] in, input [5:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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8: out = in[8];
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9: out = in[9];
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10: out = in[10];
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11: out = in[11];
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12: out = in[12];
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13: out = in[13];
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14: out = in[14];
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15: out = in[15];
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16: out = in[16];
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17: out = in[17];
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18: out = in[18];
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19: out = in[19];
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20: out = in[20];
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21: out = in[21];
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22: out = in[22];
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23: out = in[23];
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24: out = in[24];
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25: out = in[25];
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26: out = in[26];
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27: out = in[27];
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28: out = in[28];
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29: out = in[29];
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30: out = in[30];
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31: out = in[31];
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32: out = in[32];
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33: out = in[33];
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34: out = in[34];
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35: out = in[35];
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36: out = in[36];
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37: out = in[37];
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38: out = in[38];
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39: out = in[39];
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40: out = in[40];
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41: out = in[41];
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42: out = in[42];
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43: out = in[43];
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44: out = in[44];
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45: out = in[45];
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46: out = in[46];
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47: out = in[47];
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48: out = in[48];
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49: out = in[49];
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50: out = in[50];
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51: out = in[51];
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52: out = in[52];
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53: out = in[53];
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54: out = in[54];
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55: out = in[55];
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56: out = in[56];
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57: out = in[57];
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58: out = in[58];
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59: out = in[59];
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60: out = in[60];
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61: out = in[61];
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62: out = in[62];
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63: out = in[63];
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endcase
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endmodule
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// test_simulation_mux_8_test.v
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module f6_test(input [7:0] in, input [2:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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endcase
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endmodule
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