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5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
65 lines
1.3 KiB
Verilog
65 lines
1.3 KiB
Verilog
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// test_simulation_sop_basic_10_test.v
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module f1_test(input [1:0] in, input select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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endcase
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endmodule
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// test_simulation_sop_basic_11_test.v
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module f2_test(input [3:0] in, input [1:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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endcase
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endmodule
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// test_simulation_sop_basic_12_test.v
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module f3_test(input [7:0] in, input [2:0] select, output reg out);
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always @( in or select)
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case (select)
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0: out = in[0];
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1: out = in[1];
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2: out = in[2];
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3: out = in[3];
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4: out = in[4];
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5: out = in[5];
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6: out = in[6];
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7: out = in[7];
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endcase
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endmodule
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// test_simulation_sop_basic_18_test.v
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module f4_test(input [7:0] in, output out);
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assign out = ~^in;
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endmodule
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// test_simulation_sop_basic_3_test.v
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module f5_test(input in, output out);
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assign out = ~in;
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endmodule
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// test_simulation_sop_basic_7_test.v
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module f6_test(input in, output out);
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assign out = in;
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endmodule
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// test_simulation_sop_basic_8_test.v
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module f7_test(output out);
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assign out = 1'b0;
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endmodule
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// test_simulation_sop_basic_9_test.v
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module f8_test(input in, output out);
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assign out = ~in;
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endmodule
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