yosys

mirror of https://github.com/YosysHQ/yosys synced 2026-08-03 04:43:28 +00:00

Clifford Wolf 88db09255b Added autotest -e (do not use -noexpr on write_verilog)		2014-08-30 18:34:07 +02:00
..
.gitignore
hana_vlib.v
README
run-test.sh	Added autotest -e (do not use -noexpr on write_verilog)	2014-08-30 18:34:07 +02:00
test_intermout.v
test_parse2synthtrans.v
test_parser.v
test_simulation_always.v
test_simulation_and.v
test_simulation_buffer.v
test_simulation_decoder.v
test_simulation_inc.v
test_simulation_mux.v
test_simulation_nand.v
test_simulation_nor.v
test_simulation_or.v
test_simulation_seq.v
test_simulation_shifter.v
test_simulation_sop.v
test_simulation_techmap.v
test_simulation_techmap_tech.v
test_simulation_vlib.v
test_simulation_xnor.v
test_simulation_xor.v

This test cases are copied from the hana project:
https://sourceforge.net/projects/sim-sim/