mirror of
https://github.com/YosysHQ/yosys
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b98376884e
These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine. |
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| .. | ||
| .gitignore | ||
| add_sub.ys | ||
| adffs.ys | ||
| bug1597.ys | ||
| bug1598.ys | ||
| bug1626.ys | ||
| bug1644.il.gz | ||
| bug1644.ys | ||
| bug2061.ys | ||
| counter.ys | ||
| dffs.ys | ||
| dpram.v | ||
| dpram.ys | ||
| fsm.ys | ||
| ice40_dsp.ys | ||
| ice40_opt.ys | ||
| ice40_wrapcarry.ys | ||
| latches.ys | ||
| logic.ys | ||
| macc.v | ||
| macc.ys | ||
| memories.ys | ||
| mul.ys | ||
| mux.ys | ||
| rom.v | ||
| rom.ys | ||
| run-test.sh | ||
| shifter.ys | ||
| tribuf.ys | ||