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Most of the word/coarse level cells have an assigned group and individual page. The gate/fine level cells are all on one page. Fix links to `cell_library.rst`.
138 lines
4.1 KiB
ReStructuredText
138 lines
4.1 KiB
ReStructuredText
.. role:: verilog(code)
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:language: Verilog
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Debugging cells
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---------------
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The `$print` cell is used to log the values of signals, akin to (and
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translatable to) the ``$display`` and ``$write`` family of tasks in Verilog. It
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has the following parameters:
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``FORMAT``
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The internal format string. The syntax is described below.
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``ARGS_WIDTH``
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The width (in bits) of the signal on the ``ARGS`` port.
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``TRG_ENABLE``
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True if triggered on specific signals defined in ``TRG``; false if triggered
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whenever ``ARGS`` or ``EN`` change and ``EN`` is 1.
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If ``TRG_ENABLE`` is true, the following parameters also apply:
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``TRG_WIDTH``
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The number of bits in the ``TRG`` port.
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``TRG_POLARITY``
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For each bit in ``TRG``, 1 if that signal is positive-edge triggered, 0 if
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negative-edge triggered.
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``PRIORITY``
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When multiple `$print` or `$check` cells fire on the same trigger, they
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execute in descending priority order.
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Ports:
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``TRG``
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The signals that control when this `$print` cell is triggered.
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If the width of this port is zero and ``TRG_ENABLE`` is true, the cell is
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triggered during initial evaluation (time zero) only.
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``EN``
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Enable signal for the whole cell.
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``ARGS``
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The values to be displayed, in format string order.
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.. autocellgroup:: debug
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:members:
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:source:
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:linenos:
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Format string syntax
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~~~~~~~~~~~~~~~~~~~~
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The format string syntax resembles Python f-strings. Regular text is passed
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through unchanged until a format specifier is reached, starting with a ``{``.
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Format specifiers have the following syntax. Unless noted, all items are
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required:
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``{``
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Denotes the start of the format specifier.
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size
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Signal size in bits; this many bits are consumed from the ``ARGS`` port by
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this specifier.
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``:``
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Separates the size from the remaining items.
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justify
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``>`` for right-justified, ``<`` for left-justified.
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padding
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``0`` for zero-padding, or a space for space-padding.
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width\ *?*
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(optional) The number of characters wide to pad to.
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base
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* ``b`` for base-2 integers (binary)
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* ``o`` for base-8 integers (octal)
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* ``d`` for base-10 integers (decimal)
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* ``h`` for base-16 integers (hexadecimal)
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* ``c`` for ASCII characters/strings
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* ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and
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:verilog:`$realtime`)
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For integers, this item may follow:
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``+``\ *?*
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(optional, decimals only) Include a leading plus for non-negative numbers.
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This can assist with symmetry with negatives in tabulated output.
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signedness
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``u`` for unsigned, ``s`` for signed. This distinction is only respected
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when rendering decimals.
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ASCII characters/strings have no special options, but the signal size must be
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divisible by 8.
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For simulation time, the signal size must be zero.
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Finally:
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``}``
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Denotes the end of the format specifier.
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Some example format specifiers:
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+ ``{8:>02hu}`` - 8-bit unsigned integer rendered as hexadecimal,
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right-justified, zero-padded to 2 characters wide.
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+ ``{32:< 15d+s}`` - 32-bit signed integer rendered as decimal, left-justified,
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space-padded to 15 characters wide, positive values prefixed with ``+``.
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+ ``{16:< 10hu}`` - 16-bit unsigned integer rendered as hexadecimal,
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left-justified, space-padded to 10 characters wide.
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+ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters
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wide.
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To include literal ``{`` and ``}`` characters in your format string, use ``{{``
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and ``}}`` respectively.
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It is an error for a format string to consume more or less bits from ``ARGS``
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than the port width.
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Values are never truncated, regardless of the specified width.
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Note that further restrictions on allowable combinations of options may apply
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depending on the backend used.
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For example, Verilog does not have a format specifier that allows zero-padding a
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string (i.e. more than 1 ASCII character), though zero-padding a single
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character is permitted.
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Thus, while the RTLIL format specifier ``{8:>02c}`` translates to ``%02c``,
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``{16:>02c}`` cannot be represented in Verilog and will fail to emit. In this
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case, ``{16:> 02c}`` must be used, which translates to ``%2s``.
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