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This does not correctly handle an `$overwrite_tag` on a module output, but since we currently require the user to flatten the design for cross-module dft, this cannot be observed from within the design, only by manually inspecting the signals in the design. |
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.. | ||
binding.cc | ||
binding.h | ||
bitpattern.h | ||
calc.cc | ||
cellaigs.cc | ||
cellaigs.h | ||
celledges.cc | ||
celledges.h | ||
celltypes.h | ||
consteval.h | ||
constids.inc | ||
cost.h | ||
driver.cc | ||
ff.cc | ||
ff.h | ||
ffinit.h | ||
ffmerge.cc | ||
ffmerge.h | ||
fmt.cc | ||
fmt.h | ||
fstdata.cc | ||
fstdata.h | ||
hashlib.h | ||
json.cc | ||
json.h | ||
log.cc | ||
log.h | ||
macc.h | ||
mem.cc | ||
mem.h | ||
modtools.h | ||
qcsat.cc | ||
qcsat.h | ||
register.cc | ||
register.h | ||
rtlil.cc | ||
rtlil.h | ||
satgen.cc | ||
satgen.h | ||
sigtools.h | ||
timinginfo.h | ||
utils.h | ||
yosys.cc | ||
yosys.h | ||
yw.cc | ||
yw.h |