mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
7 lines
152 B
Plaintext
7 lines
152 B
Plaintext
read_verilog -sv -mem2reg mem_bounds.sv
|
|
proc
|
|
flatten
|
|
opt -full
|
|
select -module top
|
|
sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
|