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c77b7343d0
* Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct. |
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| .. | ||
| .gitignore | ||
| abc9_map.v | ||
| abc9_model.v | ||
| abc9_unmap.v | ||
| adff2dff.v | ||
| cellhelp.py | ||
| cells.lib | ||
| cmp2lcu.v | ||
| cmp2lut.v | ||
| dff2ff.v | ||
| gate2lut.v | ||
| gen_fine_ffs.py | ||
| Makefile.inc | ||
| mul2dsp.v | ||
| pmux2mux.v | ||
| prep.cc | ||
| simcells.v | ||
| simlib.v | ||
| synth.cc | ||
| techmap.v | ||