yosys/tests/sva/sva_value_change_rose.sv at c6e96d78166792c44ff0772908d27aeaef6d9888 - mirrors/yosys - Libre-Chip.org

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Jannis Harder a855d62b42 verific: Improve logic generated for SVA value change expressions

The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).

This patch now generates logic that at the same time

	a) provides the expected behavior in a 2-valued logic setting, not
	   depending on any dont-care optimizations, and

	b) properly handles 'x values in yosys simulation

2022-05-09 15:04:01 +02:00

20 lines

245 B

Systemverilog

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 module top (
 	input clk,
 	input a, b
 );
 	default clocking @(posedge clk); endclocking
     wire a_copy;
     assign a_copy = a;
 	assert property (
 		$rose(a) |-> b
 	);
 `ifndef FAIL
 	assume property (
 		$rose(a_copy) |-> b
 	);
 `endif
 endmodule