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145 lines
2.9 KiB
Verilog
145 lines
2.9 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module macc_simple (
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input wire clk,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [8:0] Z
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);
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always @(posedge clk)
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Z <= Z + (A * B);
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endmodule
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module macc_simple_clr (
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input wire clk,
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input wire clr,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [6:0] Z
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);
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always @(posedge clk)
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if (clr) Z <= (A * B);
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else Z <= Z + (A * B);
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endmodule
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module macc_simple_arst (
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input wire clk,
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input wire rst,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [8:0] Z
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);
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always @(posedge clk or posedge rst)
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if (rst) Z <= 0;
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else Z <= Z + (A * B);
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endmodule
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module macc_simple_ena (
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input wire clk,
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input wire ena,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [8:0] Z
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);
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always @(posedge clk)
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if (ena) Z <= Z + (A * B);
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endmodule
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module macc_simple_arst_clr_ena (
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input wire clk,
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input wire rst,
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input wire clr,
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input wire ena,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [7:0] Z
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);
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always @(posedge clk or posedge rst)
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if (rst) Z <= 0;
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else if (ena) begin
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if (clr) Z <= (A * B);
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else Z <= Z + (A * B);
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end
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endmodule
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module macc_simple_preacc (
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input wire clk,
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input wire [4:0] A,
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input wire [4:0] B,
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output wire [7:0] Z
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);
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reg [7:0] acc;
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assign Z = acc + (A * B);
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always @(posedge clk)
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acc <= Z;
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endmodule
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module macc_simple_preacc_clr (
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input wire clk,
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input wire clr,
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input wire [5:0] A,
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input wire [5:0] B,
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output reg [7:0] Z
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);
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reg [7:0] acc;
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assign Z = (clr) ? (A * B) : (acc + (A * B));
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always @(posedge clk)
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acc <= Z;
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endmodule
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module macc_simple_signed (
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input wire clk,
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input wire signed [4:0] A,
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input wire signed [4:0] B,
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output reg signed [7:0] Z
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);
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always @(posedge clk)
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Z <= Z + (A * B);
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endmodule
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module macc_simple_signed_subtract (
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input wire clk,
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input wire signed [4:0] A,
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input wire signed [4:0] B,
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output reg signed [7:0] Z
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);
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always @(posedge clk)
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Z <= Z - (A * B);
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endmodule
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