mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-29 09:28:46 +00:00
45 lines
923 B
Tcl
45 lines
923 B
Tcl
yosys -import
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proc testcase {top} {
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log -header "Testcase $top"
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log -push
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design -load ast
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prep -top $top
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design -save gold
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design -load ast
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hierarchy -top $top
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synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
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opt_clean
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select -assert-none t:\$mul
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stat
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dump $top
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select -assert-count 1 t:QL_DSPV2_MULTACC
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read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
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prep -flatten -top $top
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design -save gate
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design -clear
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design -copy-from gate -as gate A:top
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design -copy-from gold -as gold A:top
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async2sync
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equiv_make gold gate equiv
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opt -fast equiv
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equiv_induct equiv
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equiv_status -assert equiv
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log -pop
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}
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read_verilog dspv2_macc.v
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design -save ast
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testcase "macc_simple"
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testcase "macc_simple_clr"
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testcase "macc_simple_arst"
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testcase "macc_simple_ena"
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testcase "macc_simple_arst_clr_ena"
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testcase "macc_simple_preacc_clr"
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testcase "macc_simple_signed"
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testcase "macc_simple_signed_subtract"
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