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yosys/techlibs/common
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Clifford Wolf da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
adff2dff.v
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib
cmp2lut.v cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
Makefile.inc cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
pmux2mux.v
prep.cc Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
simcells.v Fix typo. 2018-12-05 17:13:27 +00:00
simlib.v Add $allconst and $allseq cell types 2018-02-23 13:14:47 +01:00
synth.cc Merge pull request #772 from whitequark/synth_lut 2019-01-02 15:44:57 +01:00
techmap.v Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00