mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-31 11:21:31 +00:00
5 lines
78 B
Verilog
5 lines
78 B
Verilog
module test(input in, output reg out);
|
|
|
|
always @(in)
|
|
out = in;
|
|
endmodule
|