yosys/techlibs/intel_alm/common/lutram_mlab.txt at c5d096b7b8302181a1329959891e4e6b352efcdc - mirrors/yosys - Libre-Chip.org

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Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation

By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.

2020-05-07 21:03:13 +02:00

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 bram MISTRAL_MLAB
     init   0   # TODO: Re-enable when Yosys remembers the original filename.
     abits  5
     dbits  1
     groups 2
     ports  1 1
     wrmode 1 0
     # write enable
     enable 1 0
     transp 0 0
     clocks 1 0
     clkpol 1 1
 endbram
 match MISTRAL_MLAB
     min efficiency 5
     make_outreg
 endmatch