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1a07b330f8
Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
51 lines
891 B
Verilog
51 lines
891 B
Verilog
`default_nettype none
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module __MUL27X27(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 27;
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parameter B_WIDTH = 27;
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parameter Y_WIDTH = 54;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL27X27 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL18X18(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL18X18 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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module __MUL9X9(A, B, Y);
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parameter A_SIGNED = 1;
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parameter B_SIGNED = 1;
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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MISTRAL_MUL9X9 _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
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endmodule
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