Claire Xenia Wolf 46d3f03d27 Add default assignments to other SB_* simulation models ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>		2021-04-20 18:52:36 +02:00
..
tests
.gitignore
abc9_model.v
arith_map.v
brams.txt
brams_init.py
brams_map.v	verilog: significant block scoping improvements	2021-01-31 09:42:09 -05:00
cells_map.v
cells_sim.v	Add default assignments to other SB_* simulation models	2021-04-20 18:52:36 +02:00
dsp_map.v
ff_map.v	ice40: Use dfflegalize.	2020-07-05 05:12:09 +02:00
ice40_braminit.cc
ice40_opt.cc	synth_ice40: Use opt_dff.	2020-07-30 22:26:20 +02:00
latches_map.v
Makefile.inc	synth_ice40: Use opt_dff.	2020-07-30 22:26:20 +02:00
synth_ice40.cc	Blackbox all whiteboxes after synthesis	2021-03-17 21:07:20 +00:00