mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity
yosys/backends/verilog
History
Marcelina Kościelnicka c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc kernel/rtlil: Extract some helpers for checking memory cell types. 2021-05-22 21:43:00 +02:00