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yosys/techlibs/common
Clifford Wolf c4b8575f43 Add "wreduce -keepdc", fixes #1016
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
..
.gitignore
adff2dff.v
cellhelp.py
cells.lib
cmp2lut.v
dff2ff.v
gate2lut.v
Makefile.inc
pmux2mux.v
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v
simlib.v
synth.cc
techmap.v