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48 lines
2 KiB
Text
48 lines
2 KiB
Text
read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_ALUT2
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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