mirror of
https://github.com/YosysHQ/yosys
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166 lines
2.9 KiB
Verilog
166 lines
2.9 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The internal logic cell simulation library.
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*
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* This Verilog library contains simple simulation models for the internal
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* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
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* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
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*
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*/
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module _NOT_(A, Y);
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input A;
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output Y;
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assign Y = ~A;
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endmodule
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module _AND_(A, B, Y);
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input A, B;
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output Y;
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assign Y = A & B;
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endmodule
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module _OR_(A, B, Y);
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input A, B;
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output Y;
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assign Y = A | B;
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endmodule
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module _XOR_(A, B, Y);
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input A, B;
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output Y;
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assign Y = A ^ B;
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endmodule
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module _MUX_(A, B, S, Y);
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input A, B, S;
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output reg Y;
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always @* begin
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if (S)
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Y = B;
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else
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Y = A;
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end
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endmodule
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module _DFF_N_(D, Q, C);
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input D, C;
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output reg Q;
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always @(negedge C) begin
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Q <= D;
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end
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endmodule
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module _DFF_P_(D, Q, C);
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input D, C;
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output reg Q;
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always @(posedge C) begin
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Q <= D;
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end
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endmodule
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module _DFF_NN0_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(negedge C or negedge R) begin
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if (R == 0)
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Q <= 0;
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else
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Q <= D;
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end
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endmodule
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module _DFF_NN1_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(negedge C or negedge R) begin
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if (R == 0)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module _DFF_NP0_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(negedge C or posedge R) begin
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if (R == 1)
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Q <= 0;
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else
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Q <= D;
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end
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endmodule
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module _DFF_NP1_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(negedge C or posedge R) begin
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if (R == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module _DFF_PN0_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(posedge C or negedge R) begin
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if (R == 0)
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Q <= 0;
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else
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Q <= D;
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end
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endmodule
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module _DFF_PN1_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(posedge C or negedge R) begin
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if (R == 0)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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module _DFF_PP0_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(posedge C or posedge R) begin
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if (R == 1)
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Q <= 0;
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else
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Q <= D;
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end
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endmodule
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module _DFF_PP1_(D, Q, C, R);
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input D, C, R;
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output reg Q;
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always @(posedge C or posedge R) begin
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if (R == 1)
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Q <= 1;
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else
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Q <= D;
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end
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endmodule
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