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49 lines
1.8 KiB
Bash
49 lines
1.8 KiB
Bash
set -euo pipefail
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mkdir -p temp
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# Synthesize a tiny design through paths that previously round-tripped
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# src through get_src_attribute() → set_src_attribute() and broke the
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# flat-leaf invariant: opt_merge -share_all produces a Concat src on the
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# surviving cell, then opt_dff / FfData emit re-emits the cell. Before
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# the adopt_src_from refactor every pipe-joined flatten was re-interned
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# as a single pipe-containing Leaf — now those paths transfer the id
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# verbatim and no Leaf ever contains '|'.
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cat > temp/pipe.v <<'EOF'
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module top(input clk, input [7:0] a, b, c, d, output reg [7:0] x, y);
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always @(posedge clk) begin
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x <= a + b;
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y <= c + d;
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end
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endmodule
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EOF
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${YOSYS} -p "read_verilog temp/pipe.v; hierarchy -top top; proc; opt; opt_merge -share_all; alumacc; opt_dff; dump_twines" \
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> temp/pipe-dump.txt 2>&1
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if grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/pipe-dump.txt | grep -q '|'; then
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echo "FAIL: dump_twines produced a leaf containing '|':" >&2
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grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/pipe-dump.txt | grep '|' >&2
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exit 1
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fi
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# A second pattern that exercises the memory-mapping code path
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# (Mem::extract_rdff stash + FfData::emit).
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cat > temp/mem.v <<'EOF'
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module mem(input clk, input we, input [3:0] addr, input [7:0] din, output reg [7:0] dout);
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reg [7:0] m [0:15];
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always @(posedge clk) begin
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if (we) m[addr] <= din;
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dout <= m[addr];
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end
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endmodule
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EOF
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${YOSYS} -p "read_verilog temp/mem.v; hierarchy -top mem; proc; opt; memory_map; opt_dff; dump_twines" \
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> temp/mem-dump.txt 2>&1
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if grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/mem-dump.txt | grep -q '|'; then
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echo "FAIL: dump_twines (memory_map path) produced a leaf containing '|':" >&2
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grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/mem-dump.txt | grep '|' >&2
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exit 1
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fi
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