Emil J. Tywoniak c3ffbf6fae WIP		2026-06-12 00:18:53 +02:00
..
.gitignore	gatemate: Add LUT tree library script	2022-06-27 10:09:48 +01:00
arith_map.v	synth_gatemate: Initial implementation	2021-11-13 21:53:25 +01:00
brams.txt	gatemate: WRITE_THROUGH mode change	2025-04-18 14:16:02 +02:00
brams_init_20.vh	synth_gatemate: Initial implementation	2021-11-13 21:53:25 +01:00
brams_init_40.vh	synth_gatemate: Revise block RAM read modes and initialization	2021-11-13 21:53:25 +01:00
brams_map.v	gatemate: Set unused BRAM inputs to 'bx	2025-04-28 14:42:16 +02:00
cells_bb.v	gatemate: fix SERDES CDR parameters	2025-10-27 15:47:48 +01:00
cells_sim.v	Change to blocking assignments in non-clocked process.	2025-04-23 17:13:37 +02:00
gatemate_foldinv.cc	WIP	2026-06-12 00:18:53 +02:00
inv_map.v	gatemate: Add LUT tree library script	2022-06-27 10:09:48 +01:00
lut_map.v	synth_gatemate: Initial implementation	2021-11-13 21:53:25 +01:00
make_lut_tree_lib.py	gatemate: Add LUT tree library script	2022-06-27 10:09:48 +01:00
Makefile.inc	Makefile: Add gatemate genfiles	2025-11-04 11:46:27 +13:00
mul_map.v	synth_gatemate: Rename multiplier factor parameters	2021-11-13 21:53:25 +01:00
mux_map.v	synth_gatemate: Initial implementation	2021-11-13 21:53:25 +01:00
reg_map.v	gatemate: Enable register initialization	2023-02-15 17:29:01 +01:00
synth_gatemate.cc	Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5	2026-05-06 13:40:15 +00:00