mirror of
https://github.com/YosysHQ/yosys
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9396e5e5fe
The `portarcs` pass was already ignoring `$buf` cells when loading timing data, but now bufnorm will also emit `$input_port` and `$connect` helper cells, which need to be ignored as well.
319 lines
9.3 KiB
C++
319 lines
9.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/timinginfo.h"
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#include "kernel/rtlil.h"
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#include "kernel/utils.h"
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#include "kernel/celltypes.h"
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#include "kernel/log_help.h"
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PRIVATE_NAMESPACE_BEGIN
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USING_YOSYS_NAMESPACE
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static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
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{
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RTLIL::Wire *w;
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while ((w = bit.wire) != NULL && !w->port_input &&
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w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
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bit = w->driverCell()->getPort(ID::A)[bit.offset];
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}
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return bit;
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}
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struct PortarcsPass : Pass {
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PortarcsPass() : Pass("portarcs", "derive port arcs for propagation delay") {}
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bool formatted_help() override {
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auto *help = PrettyHelp::get_current();
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help->set_group("passes/status");
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return false;
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" portarcs [options] [selection]\n");
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log("\n");
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log("This command characterizes the combinational content of selected modules and\n");
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log("derives timing arcs going from module inputs to module outputs representing the\n");
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log("propagation delay of the module.\n");
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log("\n");
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log(" -draw\n");
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log(" plot the computed delay table to the terminal\n");
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log("\n");
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log(" -icells\n");
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log(" assign unit delay to gates from the internal Yosys cell library\n");
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log("\n");
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log(" -write\n");
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log(" write the computed arcs back into the module as $specify2 instances\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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{
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log_header(d, "Executing PORTARCS pass. (derive propagation arcs)\n");
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size_t argidx;
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bool icells_mode = false, write_mode = false, draw_mode = false;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-icells")
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icells_mode = true;
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else if (args[argidx] == "-write")
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write_mode = true;
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else if (args[argidx] == "-draw")
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draw_mode = true;
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else
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break;
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}
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extra_args(args, argidx, d);
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d->bufNormalize(true);
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TimingInfo tinfo(d);
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if (icells_mode) {
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CellTypes ct;
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ct.setup_stdcells_eval();
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for (auto [id, type] : ct.cell_types) {
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auto &tdata = tinfo.data[id];
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tdata.has_inputs = true;
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for (auto inp : type.inputs)
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for (auto out : type.outputs)
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tdata.comb[TimingInfo::BitBit({inp, 0}, {out, 0})] = 1000;
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}
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}
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for (auto m : d->selected_whole_modules_warn()) {
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bool ambiguous_ports = false;
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SigSpec inputs, outputs;
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for (auto port : m->ports) {
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Wire *w = m->wire(port);
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log_assert(w->port_input || w->port_output);
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if (w->port_input && w->port_output) {
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log_warning("Module '%s' with ambiguous direction on port %s ignored.\n",
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log_id(m), log_id(w));
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ambiguous_ports = true;
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break;
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}
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if (w->port_input)
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inputs.append(w);
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else
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outputs.append(w);
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}
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if (ambiguous_ports)
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continue;
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SigSpec ordering;
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{
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TopoSort<SigBit> sort;
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for (auto cell : m->cells())
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// Ignore all bufnorm helper cells
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if (!cell->type.in(ID($buf), ID($input_port), ID($connect))) {
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auto tdata = tinfo.find(cell->type);
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if (tdata == tinfo.end())
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log_cmd_error("Missing timing data for module '%s'.\n", log_id(cell->type));
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for (auto [edge, delay] : tdata->second.comb) {
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auto from = edge.first.get_connection(cell);
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auto to = edge.second.get_connection(cell);
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if (from && to) {
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auto from_c = canonical_bit(from.value());
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if (from_c.wire)
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sort.edge(from_c, to.value());
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}
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}
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}
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if (!sort.sort())
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log_error("Failed to sort instances in module %s.\n", log_id(m));
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ordering = sort.sorted;
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}
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dict<SigBit, int*> annotations;
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std::vector<std::unique_ptr<int[]>> allocated;
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std::vector<int*> recycling;
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auto alloc_for_bit = [&](SigBit bit) {
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if (!recycling.empty()) {
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annotations[bit] = recycling.back();
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recycling.pop_back();
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} else {
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int *p = new int[std::max(1, inputs.size())];
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allocated.emplace_back(p);
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annotations[bit] = p;
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}
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};
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for (auto bit : outputs) {
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SigBit bit_c = canonical_bit(bit);
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alloc_for_bit(bit_c);
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// consistency check
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annotations.at(bit_c)[0] = (intptr_t) bit_c.wire;
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}
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for (int i = ordering.size() - 1; i >= 0; i--) {
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SigBit bit = ordering[i];
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if (!bit.wire->port_input) {
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auto cell = bit.wire->driverCell();
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auto tdata = tinfo.find(cell->type);
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log_assert(tdata != tinfo.end());
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for (auto [edge, delay] : tdata->second.comb) {
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auto from = edge.first.get_connection(cell);
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auto to = edge.second.get_connection(cell);
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if (from && to && to.value() == bit) {
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auto from_c = canonical_bit(from.value());
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if (from_c.wire) {
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if (!annotations.count(from_c)) {
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alloc_for_bit(from_c);
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// consistency check
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annotations.at(from_c)[0] = (intptr_t) from_c.wire;
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} else {
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// consistency check
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log_assert(annotations.at(from_c)[0] == ((int) (intptr_t) from_c.wire));
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}
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}
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}
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}
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}
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if (annotations.count(bit)) {
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// consistency check
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log_assert(annotations.at(bit)[0] == ((int) (intptr_t) bit.wire));
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} else {
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alloc_for_bit(bit);
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}
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recycling.push_back(annotations.at(ordering[i]));
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}
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log_debug("Allocated %lux%d\n", allocated.size(), inputs.size());
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for (auto bit : outputs) {
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int *p = annotations.at(canonical_bit(bit));
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for (int i = 0; i < inputs.size(); i++)
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p[i] = -1;
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}
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for (int i = 0; i < ordering.size(); i++) {
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SigBit bit = ordering[i];
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int *p = annotations.at(bit);
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if (bit.wire->port_input) {
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for (int j = 0; j < inputs.size(); j++)
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p[j] = (j == i) ? 0 : -1;
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} else {
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for (int j = 0; j < inputs.size(); j++)
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p[j] = -1;
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auto cell = ordering[i].wire->driverCell();
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auto tdata = tinfo.find(cell->type);
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log_assert(tdata != tinfo.end());
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for (auto [edge, delay] : tdata->second.comb) {
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auto from = edge.first.get_connection(cell);
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auto to = edge.second.get_connection(cell);
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if (from && to && to.value() == ordering[i]) {
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auto from_c = canonical_bit(from.value());
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if (from_c.wire) {
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int *q = annotations.at(from_c);
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for (int j = 0; j < inputs.size(); j++)
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if (q[j] >= 0)
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p[j] = std::max(p[j], q[j] + delay);
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}
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}
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}
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}
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}
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if (draw_mode) {
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auto bit_str = [](SigBit bit) {
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return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
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};
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std::vector<std::string> headings;
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int top_length = 0;
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for (auto bit : inputs) {
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headings.push_back(bit_str(bit));
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top_length = std::max(top_length, (int) headings.back().size());
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}
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int max_delay = 0;
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for (auto bit : outputs) {
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int *p = annotations.at(canonical_bit(bit));
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for (auto i = 0; i < inputs.size(); i++)
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if (p[i] > max_delay)
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max_delay = p[i];
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}
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log("Delay legend:\n\n");
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log(" ");
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for (int i = 0; i < 24; i++)
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log("\033[48;5;%dm ", 232+i);
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log("\033[0m\n");
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log(" |%22s|\n", "");
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log(" 0%22s%d\n", "", max_delay);
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log("\n");
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for (int k = top_length - 1; k >= 0; k--) {
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log(" %10s ", "");
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for (auto &h : headings)
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log("%c", (k < (int) h.size()) ? h[k] : ' ');
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log("\n");
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}
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log("\n");
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for (auto bit : outputs) {
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log(" %10s ", bit_str(bit));
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int *p = annotations.at(canonical_bit(bit));
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for (auto i = 0; i < inputs.size(); i++)
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log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay);
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log("\033[0m\n");
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}
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}
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if (write_mode) {
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for (auto bit : outputs) {
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int *p = annotations.at(canonical_bit(bit));
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for (auto i = 0; i < inputs.size(); i++) {
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if (p[i] >= 0) {
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Cell *spec = m->addCell(NEW_ID, ID($specify2));
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spec->setParam(ID::SRC_WIDTH, 1);
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spec->setParam(ID::DST_WIDTH, 1);
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spec->setParam(ID::T_FALL_MAX, p[i]);
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spec->setParam(ID::T_FALL_TYP, p[i]);
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spec->setParam(ID::T_FALL_MIN, p[i]);
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spec->setParam(ID::T_RISE_MAX, p[i]);
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spec->setParam(ID::T_RISE_TYP, p[i]);
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spec->setParam(ID::T_RISE_MIN, p[i]);
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spec->setParam(ID::SRC_DST_POL, false);
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spec->setParam(ID::SRC_DST_PEN, false);
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spec->setParam(ID::FULL, false);
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spec->setPort(ID::EN, Const(1, 1));
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spec->setPort(ID::SRC, inputs[i]);
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spec->setPort(ID::DST, bit);
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}
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}
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}
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}
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}
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d->bufNormalize(false);
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}
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} PortarcsPass;
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PRIVATE_NAMESPACE_END
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