3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
yosys/frontends/ast
whitequark c34d7b13f4 ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
  reg [`WIDTH:0] mem [0:`DEPTH];
  integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.

After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.

As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
..
ast.cc Use "(id)" instead of "id" for types as temporary hack 2019-10-14 05:24:31 +02:00
ast.h ast: Add support for $sformatf system function 2020-01-19 21:20:17 +00:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc sv: Switch parser to glr, prep for typedef 2019-10-03 09:54:14 +01:00
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
simplify.cc ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. 2020-02-07 00:41:54 +00:00