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24 lines
450 B
Verilog
24 lines
450 B
Verilog
module bram #(
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parameter ABITS = 8, DBITS = 8,
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parameter INIT_ADDR = 0, INIT_DATA = 0
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) (
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input clk,
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input [ABITS-1:0] WR_ADDR,
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input [DBITS-1:0] WR_DATA,
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input WR_EN,
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input [ABITS-1:0] RD_ADDR,
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output reg [DBITS-1:0] RD_DATA
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);
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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initial begin
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memory[INIT_ADDR] <= INIT_DATA;
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end
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always @(posedge clk) begin
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if (WR_EN) memory[WR_ADDR] <= WR_DATA;
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RD_DATA <= memory[RD_ADDR];
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end
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endmodule
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