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10 lines
389 B
Plaintext
10 lines
389 B
Plaintext
read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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flatten
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equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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select -assert-count 3 t:FACADE_IO
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select -assert-none t:FACADE_IO %% t:* %D
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