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Code Activity
yosys/frontends/verilog
History
Xing Guo c30fd46ea3 Fix handling of cases that look like sva labels again. 
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
2025-09-05 11:54:13 +08:00
..
.gitignore read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
const2ast.cc const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Makefile.inc verilog: fix build dependency graph 2025-08-11 13:34:10 +02:00
preproc.cc preproc: formatting 2025-08-11 13:34:10 +02:00
preproc.h preproc: formatting 2025-08-11 13:34:10 +02:00
verilog_error.cc verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
verilog_error.h verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
verilog_frontend.cc verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
verilog_frontend.h const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
verilog_lexer.h verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
verilog_lexer.l verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
verilog_location.h verilog: Fix missing sstream include 2025-08-21 08:26:20 +01:00
verilog_parser.y Fix handling of cases that look like sva labels again. 2025-09-05 11:54:13 +08:00