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22 lines
299 B
Verilog
22 lines
299 B
Verilog
module top
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(
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input [7:0] data_a,
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input [6:1] addr_a,
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input we_a, clk,
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output reg [7:0] q_a
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);
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// Declare the RAM variable
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reg [7:0] ram[63:0];
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// Port A
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always @ (posedge clk)
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begin
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if (we_a)
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begin
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ram[addr_a] <= data_a;
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q_a <= data_a;
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end
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q_a <= ram[addr_a];
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end
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endmodule
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