mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
16 lines
252 B
Verilog
16 lines
252 B
Verilog
module dff
|
|
( input d, clk, output reg q );
|
|
always @( posedge clk )
|
|
q <= d;
|
|
endmodule
|
|
|
|
module dffe
|
|
( input d, clk, en, output reg q );
|
|
initial begin
|
|
q = 0;
|
|
end
|
|
always @( posedge clk )
|
|
if ( en )
|
|
q <= d;
|
|
endmodule
|