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70 lines
2.6 KiB
Text
70 lines
2.6 KiB
Text
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# no uram by default
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design -reset
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top priority_memory
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select -assert-none t:URAM288
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# uram parameter
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design -reset
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read -define USE_HUGE
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top priority_memory -noiopad
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select -assert-count 1 t:URAM288
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# uram option
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design -reset
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top priority_memory -noiopad -uram
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# check for URAM block
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select -assert-count 1 t:URAM288
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# check port A in code maps to port A in hardware:
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# %co:+[DOUT_A] selects everything connected to a URAM288.DOUT_A port
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# w:rdata_a selects the wire rdata_a
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# %i finds the intersection of the two above selections
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# if the result is 1 then the wire rdata_a is connected to Port A correctly
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select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
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# we expect no more than 2 LUT2s to control the hardware priority
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# if there are extra LUTs, then it is likely emulating logic it shouldn't
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# ignore anything using blif, since that doesn't seem to support priority logic
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# and is indicative of using verific/tabby
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select -assert-max 2 t:LUT* n:*blif* %d
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# reverse priority
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design -reset
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read -define FLIP_PORTS
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top priority_memory -noiopad -uram
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# test priority is mapped correctly, rdata_a should now be connected to Port B
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# see above for details
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select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
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# sp write first
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design -reset
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top sp_write_first -noiopad
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select -assert-count 1 t:URAM288
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# write first connects rdata_a to port B
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# similar to above, but also tests that rdata_a *isn't* connected to port A
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select -assert-none 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
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select -assert-count 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
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# sp read first
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design -reset
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top sp_read_first -noiopad
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select -assert-count 1 t:URAM288
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# read first connects rdata_a to port A
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# see above for details
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select -assert-count 1 t:URAM288 %co:+[DOUT_A] w:rdata_a %i
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select -assert-none 1 t:URAM288 %co:+[DOUT_B] w:rdata_a %i
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# sp read or write for size 2048 x 144b
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# the two URAM ports A and B are concatenated, with port A serving LSBs and port B serving MSBs
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design -reset
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read_verilog priority_memory.v
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synth_xilinx -family xcup -top sp_read_or_write -noiopad
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select -assert-count 1 t:URAM288
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# we expect no more than 1 LUT2 to control the hardware enable ports
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# see above for details about this command
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select -assert-max 1 t:LUT* n:*blif* %d
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