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26 lines
812 B
Text
26 lines
812 B
Text
# Verify src attributes survive abc when node_retention is enabled, including
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# the LUT-mapped &put path (Abc_NtkFromMappedGia*) which previously dropped
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# Silimate node-retention origins for reconstructed internal nodes.
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read_verilog <<EOT
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module t(a, b, c, d, e, f, y);
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input a, b, c, d, e, f;
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output y;
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wire t1 = a & b & c;
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wire t2 = d | e | f;
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wire t3 = t1 ^ t2;
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wire t4 = (a | d) & (b | e) & (c | f);
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assign y = t3 ^ t4;
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endmodule
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EOT
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hierarchy -top t
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proc
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opt_clean
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techmap
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aigmap
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scratchpad -set abc.node_retention 1
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# Force LUT mapping so &put uses Abc_NtkFromMappedGia (not cell-mapped &nf).
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abc -g AND,OR,XOR -script +&get,-n;&st;&if,-g,-K,4;&put
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# Every post-abc cell must carry a src attribute remapped from node retention.
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select -assert-min 1 t:*
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select -assert-count 0 t:* a:src %d
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