Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis)		2017-11-23 08:51:38 +01:00
..
ast	Remove some dead code	2017-10-10 12:00:48 +02:00
blif	Increase maximum LUT size in blifparse to 12 bits	2017-09-27 15:27:42 +02:00
ilang	Added avail params to ilang format, check module params in 'hierarchy -check'	2016-10-22 11:05:49 +02:00
json	Parse reals as string in JSON front-end	2017-09-26 14:37:03 +02:00
liberty	Added liberty parser support for types within cell decls	2016-09-23 13:53:23 +02:00
verific	Remove all PSL support code from verific.cc	2017-10-20 13:14:04 +02:00
verilog	Add Verilog "automatic" keyword (ignored in synthesis)	2017-11-23 08:51:38 +01:00