3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-14 09:56:16 +00:00
yosys/techlibs/common
Clifford Wolf 95944eb69e make all vector-size related integer params in $mem sim model signed
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
..
adff2dff.v
blackbox.sed
cells.lib
Makefile.inc
pmux2mux.v
simcells.v
simlib.v make all vector-size related integer params in $mem sim model signed 2015-04-05 17:26:53 +02:00
synth.cc
techmap.v